The present inventive concept relates to a semiconductor device, and more specifically, to a three-dimensional semiconductor memory device.
Recently, increasing the integration degree of semiconductor devices is required to satisfy the increasing user demand for performance and low price. In semiconductor memory devices, since the integration degree is a significant factor in cost, it is especially important to increase the integration degree. In traditional two-dimensional or planar semiconductor memory devices, since the integration degree is determined by an amount of circuit area occupied by a unit memory cell, techniques for forming fine patterns have a great influence on the cost of semiconductor memory devices. However, since very expensive equipment is required to produce hyper-fine patterns, although the integration degree of two-dimensional memory semiconductor devices is increasing, this increase in integration degree is limited by the equipment cost.
As alternatives for overcoming these limitations, developments have been made on techniques for forming three-dimensional memory cells. According to these techniques, since the memory cells are formed three-dimensionally, the area of semiconductor substrate is more efficiently utilized. As a result, the integration degree may be greatly increased as compared to the traditional two-dimensional memory semiconductor devices. In addition, using these techniques, word lines are formed by using a patterning process to define an active region, thereby greatly reducing a manufacturing cost per stored memory bit.